1. Field of the Invention
The present invention relates to a semiconductor storage device with capacitors, such as DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
One of well-known conventional semiconductor storage devices is a DRAM cell that is composed of a MOS (Metal-Oxide Semiconductor) transistor and a capacitor having a lower electrode of impurity diffusion layer connected to a source/drain region of the MOS transistor (as disclosed for example in Japanese Patent Application Laid-open Nos. 2004-527901 and 2004-311853). A DRAM cell disclosed in Japanese Patent Application Laid-open No. 2004-527901 includes an isolation insulating film (field dielectric layer) formed in the upper surface of a semiconductor substrate and having a recess (cavity) formed in its upper portion. The recess exposes the sidewall of the semiconductor substrate. The capacitor of the DRAM cell extends to the exposed sidewall in the recess, thereby increasing its effective area and accordingly its capacity.
The DRAM cell disclosed in Japanese Patent Application Laid-open No. 2004-527901 has thick sidewalls on the side surfaces of a gate electrode of the MOS transistor and on the side surfaces of an upper electrode of the capacitor, so that the upper portion of the source/drain region of the MOS transistor which is connected to the capacitor, is completely covered with those sidewalls. This prevents silicidation of the upper surface of that source/drain region to reduce resistance between the MOS transistor and the capacitor. It inhibits high-speed operation of the semiconductor storage device.
On the other hand, Japanese Patent Application Laid-open No. 2004-311853 discloses a DRAM cell structure in which sidewalls on the side surfaces of a gate electrode of a MOS transistor and sidewalls on the side surfaces of an upper electrode of a capacitor are spaced from each other, and a silicide layer is formed on source/drain regions of the MOS transistor to reduce resistance.
However, the DRAM cell disclosed in Japanese Patent Application Laid-open No. 2004-311853 has a possibility that polysilicon forming the upper electrode of the capacitor may be exposed between adjacent DRAM cells, depending on the width of a recess formed in an isolation insulating film and the widths of the upper electrode and its sidewalls of the capacitor (the detail of which will be described later (cf. FIGS. 14A, 14B and 15A, 15B). In that case, during the step of siliciding the upper portion of the source/drain regions of the MOS transistor, the exposed polysilicon and the upper portion of the source/drain regions may form an integral silicide layer. This will cause a short between the DRAM cells through the silicide layer, thereby decreasing the operational reliability of the semiconductor storage device.